1. Technical Field
The present invention relates to methods for manufacturing a semiconductor device and, in particular, is preferably applied to a method for manufacturing a field-effect transistor formed on a silicon-on-insulator (SOI) substrate.
2. Related Art
The availability of field-effect transistors formed on SOI substrates has been attracting a great deal of attention because of their effectiveness in device isolation, latchup-free property, small source/drain junction capacitance, etc. Especially, fully depleted SOI transistors have low power consumption and are capable of high-speed operation, which enables easy low-voltage operation. Much research for achieving the SOI transistor operation in fully depleted mode has been in progress. In such research, SOI substrates such as separation-by-implanted-oxygen (SIMOX) substrates, wafer bonding, etc. are used, as disclosed in the following patent applications: JP-A-2002-299591; and JP-A-2000-124092.
Further, in “Separation by Bonding Si Islands (SBSI) for LSI Application”, by T. Sakai et al., Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004) (hereinafter “Sakai”), a method that achieves a low-cost formation of SOI transistors by forming a SOI layer on a bulk substrate has been disclosed. In the method disclosed Sakai, after depositing Si/SiGe layers on a Si substrate, a cavity is formed between the Si substrate and the Si layer by selectively removing only the SiGe layer using the difference in the selection ratios of Si and SiGe. Further, by performing thermal oxidation of the Si that is exposed in the cavity, an SiO2 layer is buried between the Si substrate and the Si layer to form a BOX layer between the Si substrate and the Si layer.
In the above method disclosed in Sakai, a SOI transistor and a bulk transistor can simultaneously be formed on a single wafer. An SiGe layer is deposited only in a SOI transistor-forming region, not all over the wafer, by means of selective epitaxial growth. When an SiGe layer is deposited in a SOI transistor-forming region by means of selective epitaxial growth, an alignment mark used for mask positioning on the SOI transistor-forming region in the subsequent step is also formed by means of selective epitaxial growth of the SiGe layer. Further, by positioning a mask on the SOI transistor-forming region with reference to the alignment mark, the position of a device to be formed in the SOI transistor-forming region can be specified.
However, the alignment mark used for mask positioning on the SOI transistor-forming region has an Si/SiGe/Si configuration. Further, the alignment mark area becomes so large, depending on circumstances, that the SiGe of the alignment mark cannot completely be removed in removing the SiGe in the SOI transistor-forming region by means of etching. Furthermore, if any SiGe remains on the wafer, Ge is dispersed into the SOI layer in the subsequent heat treatment step, which causes not only the property degradation of devices to be formed on the SOI layer but also the Ge contamination of semiconductor manufacturing equipment, leading to a further Ge contamination of other wafers to be processed in the contaminated semiconductor manufacturing equipment.
On the other hand, even when the alignment mark having the Si/SiGe/Si configuration is small enough that the SiGe of the alignment mark can completely be removed in removing the SiGe in the SOI transistor-forming region by means of etching, the Si layer on the SiGe layer is lifted off to become a cause of particle generation.